AMD builds processors out of chiplets — small, specialized dies connected by Infinity Fabric — so a laptop, a workstation, and a server rack can all draw from the same silicon, scaled to exactly what the job needs.
Compute chiplets, I/O dies, and cache stacks combine differently depending on the job — a mobile chip built for battery life, a desktop chip built for frame rates, a server chip built to fill a rack with cores.
Two compute chiplets (CCDs) around a central I/O die, one topped with a 3D V-Cache stack — for heavy multitasking, rendering, and competitive frame rates.
A single monolithic die — no chiplet links to power — tuned for battery life, with an on-die NPU for local AI workloads on the go.
Up to twelve compute chiplets ringed around a central I/O die — density and memory bandwidth built for AI-scale infrastructure.
Each generation is a real jump in instructions-per-clock and efficiency. This is the sequence, in the order it shipped.
First chiplet design at scale. Shipped in Ryzen 3000.
Move to 5nm and DDR5. Shipped in Ryzen 7000.
Density-optimized core for EPYC Bergamo's core count.
Rebuilt front end & wider execution — current generation.
Next architecture, in design and validation today.
Talk to our team about processors, EPYC deployments, or volume orders.